The invention relates to an apparatus for furnishing instructions in a microprocessor with a multi-stage pipeline processing unit, the processing of which at least includes a "fetch instruction" phase, a "decode instruction" phase and an "execute instruction" phase, including an address register, the contents of which point to an instruction to be processed in a memory, the instruction being loaded during an instruction loading phase into an associated instruction register having an arithmetic calculation unit for calculating addresses, means for incrementing the address register contents, and a multiplexer for selecting the calculated address or the incremented successor address.
The demands made of microprocessors or microcontrollers increase with each generation of development, so that modern microprocessors are provided with processing units that previously were typical only in mainframe systems. One of the processing units makes it possible to process instructions quasi-parallel. The microprocessor or microcontroller includes so-called pipeline architecture for such a purpose. One such pipeline architecture is described in the publication Elektronik [Electronics], No. 2, January 1990, pp. 46 ff. Normally, a plurality of steps are required to carry out one instruction. In pipeline architecture, such steps are subdivided into the most equal possible substeps. Each substep can then be processed autonomously, or in other words independently of the other substeps. In order to carry out an instruction completely, the execution must run through all of the substeps sequentially. Typically, processors have three to five-stage pipelines. A three-stage pipeline will be described below:
1. Fetch: fetch an instruction. An instruction is fetched from the internal or external memory, based on the address in the program counter. PA1 2. Decode: decode an instruction. During such a phase, the operands required are fetched from the internal or external memory. The instruction to be processed at a given time is also decoded. Data that a previous instruction has generated are likewise made available to the instruction to be processed. PA1 3. Execute: carry out an instruction. Taking into account the signals that were generated during the decoding phase, the arithmetic logic unit or other execution units (such as shifters or multipliers) carry out the desired calculation. During the second phase of such a stage, the result is written back in the internal or external memory.
Each of the above stages can naturally be broken down into even more substages. When successive instructions are carried out, the pipeline is filled from clock cycle to clock cycle, on the principle of a production line. Once the pipeline is completely filled, then virtually only one more clock cycle is needed to carry out an instruction. That is naturally true only when correspondingly long programs are carried out. The above-described three-stage pipeline accordingly makes it possible to carry out instructions three times as fast as in previous microprocessors. Naturally, such an increase in performance is achieved only if the instructions follow one another sequentially. If a jump instruction occurs while the instruction is being carried out, that interrupts the flow through the pipeline, since the address of the next instruction to be processed can be ascertained only during the decoding phase. Since jump instructions, in many applications, represent a major proportion of the instructions of a microprocessor or microcontroller that are carried out, especially in the case of program loops, the increase in performance by the factor of three cannot always be assured during the running of the program.
A previous solution to the problem is known as "delayed branching". Upon the appearance of a jump instruction, a so-called "no operation" instruction NOP is always appended. As a result of the delayed processing of the actual jump target instruction, the correct target instruction is always loaded, since there is enough time to calculate the target address. The disadvantage is that when jump instructions occur, one cycle is basically lost. Instead of the "no operation" instruction, some other instruction included in the program course may be preferred under some circumstances. However, that instruction must have no influence on the jump instruction and must meet certain conditions, which severely limit the selection of such an instruction.
It is accordingly an object of the invention to provide an apparatus for furnishing instructions in a microprocessor, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type, which has a multi-stage pipeline processing unit and which makes it possible to process jump instructions in loops, with the least possible loss of speed.